//------------------------------------------------
// toppipelined.v
//
// James Forrest, 2013
// Based on code by:
// David_Harris@hmc.edu 9 November 2005
//
// Top level system including MIPS pipelined
// processor and external data and instruction
// memories
//------------------------------------------------

module dmem(input         clk, we,
            input  [31:0] a, wd,
            output [31:0] rd);

  reg  [31:0] RAM[31:0];

  assign rd = RAM[a[6:2]]; // word aligned, wrapped to 6 bits

  always @(posedge clk)
    if (we)
      RAM[a[6:2]] <= wd;
endmodule

// imem may be created with CoreGen for Xilinx synthesis
// or loaded from imem.v for simulation